On Fri, 25 Oct 2024 11:49:35 +0200, Angelo Dureghello wrote: > From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > Add a new compatible and related bindigns for the fpga-based > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > mainly to reach high speed transfer rates using a QSPI DDR > (dobule-data-rate) interface. > > The ad3552r device is defined as a child of the AXI DAC, that in > this case is acting as an SPI controller. > > Note, #io-backend is present because it is possible (in theory anyway) > to use a separate controller for the control path than that used > for the datapath. > > Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > --- > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- > 1 file changed, 66 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
