On 17.10.2024 5:00 AM, Jie Gan wrote: > Add following coresight components on QCS615, EUD, TMC/ETF, TPDM, dynamic > Funnel, TPDA, Replicator and ETM. > > Signed-off-by: Jie Gan <quic_jiegan@xxxxxxxxxxx> > --- > Already checked by command:dtbs_check W=1. > > Dependencies: > 1. Depends on qcs615 base dtsi change: > https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@xxxxxxxxxxx/ > 2. Depends on qcs615 AOSS_QMP change: > https://lore.kernel.org/linux-arm-msm/20241017025313.2028120-4-quic_chunkaid@xxxxxxxxxxx/ > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 1632 ++++++++++++++++++++++++++ > 1 file changed, 1632 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 856b40e20cf3..87cca5de018e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -202,6 +202,18 @@ l3_0: l3-cache { > }; > }; > > + dummy_eud: dummy_sink { Node names (after the ':' and before the '{' signs) can't contain underscores, use '-' instead. [...] > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x0 0x6002000 0x0 0x1000>, Please pad the non-zero address part to 8 hex digits with leading zeroes, across the board This looks like a lot of nodes, all enabled by default. Will this run on a production-fused device? Konrad
