On Sat, Oct 19, 2024 at 07:26:41PM +0300, Dmitry Baryshkov wrote: > Describe the last level cache controller on the SAR2130P and SAR1130P > platforms. They have 2 banks and also a separate register set to control > scratchpad slice. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > .../devicetree/bindings/cache/qcom,llcc.yaml | 28 ++++++++++++++++++++++ > 1 file changed, 28 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
