On Mon, Oct 21, 2024 at 04:03:57PM GMT, Melody Olvera wrote:
[..]
> diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
[..]
> +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> + .reg = 0x6b080,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_7,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_pcie_0_pipe_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .ops = &clk_regmap_mux_closest_ops,
Please confirm that the PCIe pipe clock sources should not be
&clk_regmap_phy_mux_ops, as on other platforms.
> + },
> + },
> +};
> +
[..]
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x1401c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_sdcc2_apps_clk_src",
> + .parent_data = gcc_parent_data_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_shared_ops,
Please confirm that the sdcc apps_clk_src no longer needs to use
&clk_rcg2_floor_ops.
> + },
> +};
> +
[..]
> +static struct gdsc gcc_pcie_0_gdsc = {
> + .gdscr = 0x6b004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> + .collapse_ctrl = 0x5214c,
> + .collapse_mask = BIT(0),
> + .pd = {
> + .name = "gcc_pcie_0_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
Shouldn't the PCIe GDSCs be PWRSTS_RET_ON?
> + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
> +};
> +
[..]
> +static int gcc_sm8750_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gcc_sm8750_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> + ARRAY_SIZE(gcc_dfs_clocks));
> + if (ret)
> + return ret;
> +
> + /*
> + * Keep clocks always enabled:
> + * gcc_cam_bist_mclk_ahb_clk
> + * gcc_camera_ahb_clk
> + * gcc_camera_xo_clk
> + * gcc_disp_ahb_clk
> + * gcc_eva_ahb_clk
> + * gcc_eva_xo_clk
> + * gcc_gpu_cfg_ahb_clk
> + * gcc_pcie_rscc_cfg_ahb_clk
> + * gcc_pcie_rscc_xo_clk
> + * gcc_video_ahb_clk
> + * gcc_video_xo_clk
> + */
> + regmap_update_bits(regmap, 0xa0004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x26034, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x9f004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x9f01c, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
> + regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
> + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x32038, BIT(0), BIT(0));
Any reason why qcom_branch_set_clk_en() can't be used here?
> +
> + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> + regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg,
> + BIT(14), BIT(14));
qcom_branch_set_force_mem_core() ?
Regards,
Bjorn
> +
> + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_sm8750_driver = {
> + .probe = gcc_sm8750_probe,
> + .driver = {
> + .name = "gcc-sm8750",
> + .of_match_table = gcc_sm8750_match_table,
> + },
> +};
> +
> +static int __init gcc_sm8750_init(void)
> +{
> + return platform_driver_register(&gcc_sm8750_driver);
> +}
> +subsys_initcall(gcc_sm8750_init);
> +
> +static void __exit gcc_sm8750_exit(void)
> +{
> + platform_driver_unregister(&gcc_sm8750_driver);
> +}
> +module_exit(gcc_sm8750_exit);
> +
> +MODULE_DESCRIPTION("QTI GCC SM8750 Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.46.1
>
