On Tue, Oct 08, 2024 at 05:55:27PM GMT, Subramanian Ananthanarayanan wrote: > > On 10/8/2024 5:47 PM, Subramanian Ananthanarayanan wrote: > > SA8775P has only support for SMMU v2, due to this PCIe has limited > > SID entries to enable dynamic IOMMU mapping in the driver, hence > > we are updating static entries. > > > > iommu-map entries are added to support more PCIe device like switch > > attach, SRIOV capable devices. These entries are specific to this > > board as topology of PCIe devices can vary based on the end usecase > > connected via PCIe. For other board files, these entries may > > not be directly applicable. > > > > Signed-off-by: Subramanian Ananthanarayanan <quic_skananth@xxxxxxxxxxx> > > --- > > Changes in V2: > > - Updated commit message. > > forgot to add link to v1 : https://lore.kernel.org/lkml/20241001114601.1097618-1-quic_skananth@xxxxxxxxxxx/ > Please use b4, as described on go/upstream, and you can not forget. Regards, Bjorn > -Subramanian > > > --- > > --- > > arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 62 ++++++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > > index 0c1b21def4b6..05c9f572ae42 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > > @@ -675,6 +675,37 @@ &pcie0 { > > pinctrl-names = "default"; > > pinctrl-0 = <&pcie0_default_state>; > > + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, > > + <0x100 &pcie_smmu 0x0001 0x1>, > > + <0x101 &pcie_smmu 0x0002 0x1>, > > + <0x208 &pcie_smmu 0x0003 0x1>, > > + <0x210 &pcie_smmu 0x0004 0x1>, > > + <0x218 &pcie_smmu 0x0005 0x1>, > > + <0x280 &pcie_smmu 0x0006 0x1>, > > + <0x281 &pcie_smmu 0x0007 0x1>, > > + <0x282 &pcie_smmu 0x0008 0x1>, > > + <0x283 &pcie_smmu 0x0009 0x1>, > > + <0x284 &pcie_smmu 0x000a 0x1>, > > + <0x285 &pcie_smmu 0x000b 0x1>, > > + <0x286 &pcie_smmu 0x000c 0x1>, > > + <0x287 &pcie_smmu 0x000d 0x1>, > > + <0x288 &pcie_smmu 0x000e 0x1>, > > + <0x289 &pcie_smmu 0x000f 0x1>, > > + <0x28a &pcie_smmu 0x0010 0x1>, > > + <0x28b &pcie_smmu 0x0011 0x1>, > > + <0x28c &pcie_smmu 0x0012 0x1>, > > + <0x28d &pcie_smmu 0x0013 0x1>, > > + <0x28e &pcie_smmu 0x0014 0x1>, > > + <0x28f &pcie_smmu 0x0015 0x1>, > > + <0x290 &pcie_smmu 0x0016 0x1>, > > + <0x291 &pcie_smmu 0x0017 0x1>, > > + <0x292 &pcie_smmu 0x0018 0x1>, > > + <0x293 &pcie_smmu 0x0019 0x1>, > > + <0x300 &pcie_smmu 0x001a 0x1>, > > + <0x400 &pcie_smmu 0x001b 0x1>, > > + <0x500 &pcie_smmu 0x001c 0x1>, > > + <0x501 &pcie_smmu 0x001d 0x1>; > > + > > status = "okay"; > > }; > > @@ -685,6 +716,37 @@ &pcie1 { > > pinctrl-names = "default"; > > pinctrl-0 = <&pcie1_default_state>; > > + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, > > + <0x100 &pcie_smmu 0x0081 0x1>, > > + <0x101 &pcie_smmu 0x0082 0x1>, > > + <0x208 &pcie_smmu 0x0083 0x1>, > > + <0x210 &pcie_smmu 0x0084 0x1>, > > + <0x218 &pcie_smmu 0x0085 0x1>, > > + <0x280 &pcie_smmu 0x0086 0x1>, > > + <0x281 &pcie_smmu 0x0087 0x1>, > > + <0x282 &pcie_smmu 0x0088 0x1>, > > + <0x283 &pcie_smmu 0x0089 0x1>, > > + <0x284 &pcie_smmu 0x008a 0x1>, > > + <0x285 &pcie_smmu 0x008b 0x1>, > > + <0x286 &pcie_smmu 0x008c 0x1>, > > + <0x287 &pcie_smmu 0x008d 0x1>, > > + <0x288 &pcie_smmu 0x008e 0x1>, > > + <0x289 &pcie_smmu 0x008f 0x1>, > > + <0x28a &pcie_smmu 0x0090 0x1>, > > + <0x28b &pcie_smmu 0x0091 0x1>, > > + <0x28c &pcie_smmu 0x0092 0x1>, > > + <0x28d &pcie_smmu 0x0093 0x1>, > > + <0x28e &pcie_smmu 0x0094 0x1>, > > + <0x28f &pcie_smmu 0x0095 0x1>, > > + <0x290 &pcie_smmu 0x0096 0x1>, > > + <0x291 &pcie_smmu 0x0097 0x1>, > > + <0x292 &pcie_smmu 0x0098 0x1>, > > + <0x29d &pcie_smmu 0x0099 0x1>, > > + <0x300 &pcie_smmu 0x009a 0x1>, > > + <0x400 &pcie_smmu 0x009b 0x1>, > > + <0x500 &pcie_smmu 0x009c 0x1>, > > + <0x501 &pcie_smmu 0x009d 0x1>; > > + > > status = "okay"; > > };
