On Tue 22 Oct 2024 at 11:34, Jerome Brunet <jbrunet@xxxxxxxxxxxx> wrote: > On Fri 13 Sep 2024 at 15:11, Jan Dakinevich <jan.dakinevich@xxxxxxxxxxxxxxxxx> wrote: > >> Add device tree bindings for A1 SoC audio clock and reset controllers. >> >> Signed-off-by: Jan Dakinevich <jan.dakinevich@xxxxxxxxxxxxxxxxx> >> --- >> .../clock/amlogic,axg-audio-clkc.yaml | 3 + >> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ >> .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ >> 3 files changed, 154 insertions(+) >> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h >> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> index fd7982dd4cea..df9eb8ce28dc 100644 >> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> @@ -18,6 +18,8 @@ description: >> properties: >> compatible: >> enum: >> + - amlogic,a1-audio-clkc > > This controller is missing aud_top clock input coming from the vad > controller, AFAICT. > You are passing it thourgh pclk so it is fine
