On Mon, Oct 21, 2024 at 03:16:15PM +0300, Yassine Oudjana wrote: > From: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx> > > Add device tree bindings for syscon clock and reset controllers (IMGSYS, > MFGCFG, VDECSYS and VENCSYS). > > Signed-off-by: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx> > --- > .../bindings/clock/mediatek,syscon.yaml | 4 ++++ > MAINTAINERS | 6 ++++++ > .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ > .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ > .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ > .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ > .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ > .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 10 ++++++++++ Is it really necessary to have individual files foe each of these? Seems a bit extra, no? Cheers, Conor. > 8 files changed, 72 insertions(+) > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > index 10483e26878fb..a86a64893c675 100644 > --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml > @@ -28,6 +28,10 @@ properties: > - mediatek,mt2712-mfgcfg > - mediatek,mt2712-vdecsys > - mediatek,mt2712-vencsys > + - mediatek,mt6735-imgsys > + - mediatek,mt6735-mfgcfg > + - mediatek,mt6735-vdecsys > + - mediatek,mt6735-vencsys > - mediatek,mt6765-camsys > - mediatek,mt6765-imgsys > - mediatek,mt6765-mipi0a > diff --git a/MAINTAINERS b/MAINTAINERS > index 2ce38c6c0e6ff..25484783f6a0b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14537,11 +14537,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c > F: drivers/clk/mediatek/clk-mt6735-pericfg.c > F: drivers/clk/mediatek/clk-mt6735-topckgen.c > F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h > F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h > +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h > F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h > +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h > F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h > +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h > +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > > MEDIATEK MT76 WIRELESS LAN DRIVER > M: Felix Fietkau <nbd@xxxxxxxx> > diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h > new file mode 100644 > index 0000000000000..f250c26c5eb4d > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H > +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H > + > +#define CLK_IMG_SMI_LARB2 0 > +#define CLK_IMG_CAM_SMI 1 > +#define CLK_IMG_CAM_CAM 2 > +#define CLK_IMG_SEN_TG 3 > +#define CLK_IMG_SEN_CAM 4 > +#define CLK_IMG_CAM_SV 5 > +#define CLK_IMG_SUFOD 6 > +#define CLK_IMG_FD 7 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > new file mode 100644 > index 0000000000000..d2d99a48348a0 > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h > @@ -0,0 +1,8 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H > +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H > + > +#define CLK_MFG_BG3D 0 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > new file mode 100644 > index 0000000000000..f94cec10c89ff > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H > +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H > + > +#define CLK_VDEC_VDEC 0 > +#define CLK_VDEC_SMI_LARB1 1 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ > diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h > new file mode 100644 > index 0000000000000..e5a9cb4f269ff > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h > @@ -0,0 +1,11 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H > +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H > + > +#define CLK_VENC_SMI_LARB3 0 > +#define CLK_VENC_VENC 1 > +#define CLK_VENC_JPGENC 2 > +#define CLK_VENC_JPGDEC 3 > + > +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ > diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > new file mode 100644 > index 0000000000000..c489242b226e2 > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H > +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H > + > +#define MT6735_MFG_RST0_AXI 0 > +#define MT6735_MFG_RST0_G3D 1 > + > +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ > diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > new file mode 100644 > index 0000000000000..90ad73af50a3f > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h > @@ -0,0 +1,10 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H > +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H > + > +#define MT6735_VDEC_RST0_VDEC 0 > + > +#define MT6735_VDEC_RST1_SMI_LARB1 1 > + > +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ > -- > 2.47.0 >
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