From: Laurentiu Mihalcea <laurentiu.mihalcea@xxxxxxx>
Per the current binding, QM/QXP DSPs are supposed to have 4
power domains, while the rest just 1. For QM/QXP, the 4 power
domains are: DSP, DSP_RAM, MU13A, MU13B.
First off, drop MU13A from the count as its already attached
to lsio_mu13. This decreases the count to 3.
Secondly, drop DSP and DSP_RAM from the count for QXP. These
are already attached to the DSP's LPCGs.
Thirdly, a new power domain is required for DSP-SCU communication
(MU2A). With this in mind, the number of required power domains
for QXP is 2 (MU2A, MU13B), while for QM it's 4 (MU13B, DSP,
DSP_RAM, MU2A).
Update the fsl,dsp binding to reflect all of this information.
Since the arm,mhuv2 binding has an example node using the
fsl,imx8qxp-dsp compatible, remove two of the extra PDs to
align with the required power domain count.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@xxxxxxx>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
.../devicetree/bindings/dsp/fsl,dsp.yaml | 31 +++++++++++++++----
.../bindings/mailbox/arm,mhuv2.yaml | 2 +-
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
index 9af40da5688e..ab93ffd3d2e5 100644
--- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
+++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
@@ -99,14 +99,35 @@ allOf:
contains:
enum:
- fsl,imx8qxp-dsp
- - fsl,imx8qm-dsp
- fsl,imx8qxp-hifi4
+ then:
+ properties:
+ power-domains:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-dsp
- fsl,imx8qm-hifi4
then:
properties:
power-domains:
minItems: 4
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mp-dsp
+ - fsl,imx8mp-hifi4
+ - fsl,imx8ulp-dsp
+ - fsl,imx8ulp-hifi4
+ then:
properties:
power-domains:
maxItems: 1
@@ -157,10 +178,8 @@ examples:
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
clock-names = "ipg", "ocram", "core";
- power-domains = <&pd IMX_SC_R_MU_13A>,
- <&pd IMX_SC_R_MU_13B>,
- <&pd IMX_SC_R_DSP>,
- <&pd IMX_SC_R_DSP_RAM>;
+ power-domains = <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_MU_2A>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
index a4f1fe63659a..02f06314d85f 100644
--- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
+++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
@@ -197,7 +197,7 @@ examples:
reg = <0 0x596e8000 0 0x88000>;
clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>;
clock-names = "ipg", "ocram", "core";
- power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>;
+ power-domains = <&pd 0>, <&pd 1>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx
<&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx
--
2.34.1
