On 21.10.2024 3:13 PM, Dmitry Baryshkov wrote:
> On Mon, 21 Oct 2024 at 14:04, Konrad Dybcio
> <konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:
>>
>> On 19.10.2024 6:26 PM, Dmitry Baryshkov wrote:
>>> Implement necessary support for the LLCC control on the SAR1130P and
>>> SAR2130P platforms. These two platforms use different ATTR1_MAX_CAP
>>> shift and also require manual override for num_banks.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>>> ---
>>> drivers/soc/qcom/llcc-qcom.c | 468 ++++++++++++++++++++++++++++++++++++-
>>> include/linux/soc/qcom/llcc-qcom.h | 12 +
>>> 2 files changed, 474 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>>> index a470285f54a875bf2262aac7b0f84ed8fd028ef1..ef84fe3b2af4e777126a8308bfd4ec47b28aeae2 100644
>>> --- a/drivers/soc/qcom/llcc-qcom.c
>>> +++ b/drivers/soc/qcom/llcc-qcom.c
>>> @@ -32,6 +32,7 @@
>>> #define ATTR1_FIXED_SIZE_SHIFT 0x03
>>> #define ATTR1_PRIORITY_SHIFT 0x04
>>> #define ATTR1_MAX_CAP_SHIFT 0x10
>>> +#define ATTR1_MAX_CAP_SHIFT_sar 0x0e
>>> #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
>>> #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
>>> #define ATTR0_BONUS_WAYS_SHIFT 0x10
>>> @@ -140,6 +141,11 @@ struct qcom_llcc_config {
>>> bool need_llcc_cfg;
>>> bool no_edac;
>>> bool irq_configured;
>>> + /*
>>> + * special workarounds for SAR2130P and similar platforms which have
>>> + * slightly different register mapping.
>>> + */
>>> + bool is_sar_chip;
>>
>> This is not the only odd ball, please make max_cap_width variable
>
> I'm not sure what you mean here. Moving max_cap_width to the drv_data
> / configuration? Or do you mean something else?
Match data (qcom_llcc_config) is fine, as qcom_llcc_cfg_program is only
called from .probe.
max_cap_width would be a new field that denotes the width of MAX_CAP
(which seems to always be at [31:n])
>
>>
>> [...]
>>
>>> + /*
>>> + * For some reason register returns incorrect value here.
>>> + * List compatibles instead of using .is_sar_chip since there might be
>>> + * SAR-like chips which have other number of banks.
>>> + */
>>> + if (of_device_is_compatible(dev->of_node, "qcom,sar1130p-llcc") ||
>>> + of_device_is_compatible(dev->of_node, "qcom,sar2130p-llcc")) {
>>> + num_banks = 2;
>>> + } else {
>>> + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + num_banks &= LLCC_LB_CNT_MASK;
>>> + num_banks >>= LLCC_LB_CNT_SHIFT;
>>> + }
>>>
>>> - num_banks &= LLCC_LB_CNT_MASK;
>>> - num_banks >>= LLCC_LB_CNT_SHIFT;
>>> drv_data->num_banks = num_banks;
>>
>> This too
>
> This can probably go to qcom_llcc_config.
Yep
Konrad
