On 24-10-21 09:33:20, Johan Hovold wrote:
> On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote:
> > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well.
>
> Again, this is a bit misleading as PCIe6a is using the
> 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane
> mode even if the original dtsi got this wrong.
But the lane config within the phy driver differs based on the
compatible.
>
> PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is
> a 2-lane PHY.
Wouldn't the PCIe6a also have to switch to gen4x2 compatible on a board
where PCIe6b is used?
>
> Perhaps you can rephrase this so that it doesn't sound like you are
> using compatibles to configure PCIe6a?
But currently we do configure PCIe6a based on compatibles.
What am I missing ?
>
> > So fix the resets entries for it by adding the Gen4 4-lanes compatible
> > alongside the 2-lanes one.
> >
> > Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4")
> > Reported-by: kernel test robot <lkp@xxxxxxxxx>
> > Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@xxxxxxxxx/
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
>
> Patch itself looks good.
>
> Johan
