On Sun, Oct 20, 2024 at 09:49:59PM +0800, Guodong Xu wrote:
> From: Sandie Cao <sandie.cao@xxxxxxxxxxxxxxxx>
>
> The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC.
> It is a mainboard designed for the Framework Laptop 13 Chassis, which has
> (Framework) SKU FRANHQ0001.
>
> The FML13V01 board features:
> - StarFive JH7110 SoC
> - LPDDR4 8GB
> - eMMC 32GB or 128GB
> - QSPI Flash
> - MicroSD Slot
> - PCIe-based Wi-Fi
> - 4 USB-C Ports
> - Port 1: PD 3.0 (60W Max), USB 3.2 Gen 1, DP 1.4 (4K@30Hz/2.5K@60Hz)
> - Port 2: PD 3.0 (60W Max), USB 3.2 Gen 1
> - Port 3 & 4: USB 3.2 Gen 1
>
> Create the DTS file for the DeepComputing FML13V01 board. Seven device
> nodes have been verified functional and remain enabled: i2c2, i2c5, i2c6
> qspi, mmc0, mmc1 and usb0. All others remain disabled, or are disabled
> by nodes in "jh7110-deepcomputing-fml13v01.dts".
>
> Signed-off-by: Sandie Cao <sandie.cao@xxxxxxxxxxxxxxxx>
> [elder@xxxxxxxxxxxx: revised the description, updated some nodes]
> Signed-off-by: Alex Elder <elder@xxxxxxxxxxxx>
> Signed-off-by: Guodong Xu <guodong@xxxxxxxxxxxx>
> ---
> v5: No change
> v4: Changed model string to "DeepComputing FML13V01"
> Changed dts filename and Makefile accordingly to reflect the change
> Updated device nodes status, and verified functional
> Revised the commit message
> v3: Updated the commit message
> v2: Changed the model and copmatible strings
> Updated the commit message with board features
>
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-deepcomputing-fml13v01.dts | 44 +++++++++++++++++++
> 2 files changed, 45 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 7a163a7d6ba3..b3bb12f78e7d 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -8,6 +8,7 @@ DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
>
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> new file mode 100644
> index 000000000000..b515b7d04c37
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 DeepComputing (HK) Limited
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> + model = "DeepComputing FML13V01";
> + compatible = "deepcomputing,fml13v01", "starfive,jh7110";
> +};
> +
> +&camss {
> + status = "disabled";
> +};
> +
> +&csi2rx {
> + status = "disabled";
> +};
> +
> +&gmac0 {
> + status = "disabled";
> +};
> +
> +&i2c0 {
> + status = "disabled";
> +};
> +
> +&pwm {
> + status = "disabled";
> +};
> +
> +&pwmdac {
> + status = "disabled";
> +};
> +
> +&spi0 {
> + status = "disabled";
If your board has to disable all these, then they should not have been
enabled in DTSI in the first place. Only blocks present and working in
the SoC (without amny external needs) should be enabled.
I suggest to fix that aspect first.
Best regards,
Krzysztof
