Binding requires size-cells and address-cells to be around for the SRAM.
Signed-off-by: Lothar Rubusch <l.rubusch@xxxxxxxxx>
---
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
index 7f7ac0dc1..4b19fad1e 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
@@ -684,6 +684,8 @@ nand: nand-controller@ffb90000 {
ocram: sram@ffe00000 {
compatible = "mmio-sram";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0xffe00000 0x40000>;
};
--
2.25.1
