On 10/18/24 3:27 PM, Rob Herring wrote:
On Thu, Oct 17, 2024 at 08:41:25PM +0200, Marek Vasut wrote:
The ST M24256E behaves as a regular M24C256, except for the E variant
which uses up another I2C address for Additional Write lockable page.
This page is 64 Bytes long and can contain additional data. Add entry
for it, so users can describe that page in DT. Note that users still
have to describe the main M24C256 area separately as that is on separate
I2C address from this page.
I think this should be modelled as 1 node having 2 addresses, not 2
nodes.
We had the exact same discussion regarding M24C32D, see:
https://lore.kernel.org/all/CAMRc=MdTu1gagX-L4_cHmN9aUCoKhN-b5i7yEeszKSdr+BuROg@xxxxxxxxxxxxxx/
