On Sat, Oct 19, 2024 at 12:45:42AM +0530, Taniya Das wrote:
> Add support for the display clock controller for display clients to
> be able to request for the clocks on QCS615 platform.
>
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/dispcc-qcs615.c | 786 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 796 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index bdb1c672dd90d96814b214afd234341e37e3c470..d0c815e8e4789958151742a8269d7d6f2245b26c 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -460,6 +460,15 @@ config QCM_DISPCC_2290
> Say Y if you want to support display devices and functionality such as
> splash screen.
>
> +config QCS_DISPCC_615
> + tristate "QCS615 Display Clock Controller"
> + select QCM_GCC_615
> + help
> + Support for the display clock controller on Qualcomm Technologies, Inc
> + QCS615 devices.
> + Say Y if you want to support display devices and functionality such as
> + splash screen.
> +
> config QCS_CAMCC_615
> tristate "QCS615 Camera Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index f69c1bc13d3eca1859d9e849399e55175df869c3..f2be0c678127c8f78c5ee708993ebef273d02f19 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
> obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
> +obj-$(CONFIG_QCS_DISPCC_615) += dispcc-qcs615.o
> obj-$(CONFIG_QCS_CAMCC_615) += camcc-qcs615.o
> obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
> obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
> diff --git a/drivers/clk/qcom/dispcc-qcs615.c b/drivers/clk/qcom/dispcc-qcs615.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..cc40a9a8a682ba58d9fa9db21e89a05cc75be8a5
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-qcs615.c
> @@ -0,0 +1,786 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + DT_BI_TCXO,
> + DT_GPLL0,
> + DT_DSI0_PHY_PLL_OUT_BYTECLK,
> + DT_DSI0_PHY_PLL_OUT_DSICLK,
> + DT_DSI1_PHY_PLL_OUT_DSICLK,
Is there a DSI 1 PLL on this platform?
> + DT_DP_PHY_PLL_LINK_CLK,
> + DT_DP_PHY_PLL_VCO_DIV_CLK,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_DISP_CC_PLL0_OUT_MAIN,
> + P_DP_PHY_PLL_LINK_CLK,
> + P_DP_PHY_PLL_VCO_DIV_CLK,
> + P_DSI0_PHY_PLL_OUT_BYTECLK,
> + P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_DSI1_PHY_PLL_OUT_DSICLK,
> + P_GPLL0_OUT_MAIN,
> +};
> +
--
With best wishes
Dmitry
