This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@xxxxxx>
---
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
index 5ff390915b75b..8c2cd99cf2b42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
@@ -38,7 +38,7 @@ pcie1_ep: pcie-ep@2910000 {
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 9ed6949b40e9d..b32b0ce8be462 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -57,6 +57,11 @@ phy_gmii_sel_cpsw: phy@34 {
#phy-cells = <1>;
};
+ pcie1_ctrl: pcie-ctrl@74 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x74 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@80 {
compatible = "reg-mux";
reg = <0x80 0x10>;
@@ -1398,7 +1403,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
--
2.39.2
