Add the vdosys1 display nodes to support the external display pipeline. Signed-off-by: Fei Shao <fshao@xxxxxxxxxxxx> --- Changes in v4: - Squash following patch to update MERGE alias IDs from 0-4 to 1-5: https://lore.kernel.org/all/20241014094622.1720289-1-fshao@xxxxxxxxxxxx/ arch/arm64/boot/dts/mediatek/mt8188.dtsi | 298 +++++++++++++++++++++++ 1 file changed, 298 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 09556225751e..3345a2adc0fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,9 +24,32 @@ / { #size-cells = <2>; aliases { + ethdr0 = ðdr0; gce0 = &gce0; gce1 = &gce1; + merge1 = &merge1; + merge2 = &merge2; + merge3 = &merge3; + merge4 = &merge4; + merge5 = &merge5; mutex0 = &mutex0; + mutex1 = &mutex1; + padding0 = &padding0; + padding1 = &padding1; + padding2 = &padding2; + padding3 = &padding3; + padding4 = &padding4; + padding5 = &padding5; + padding6 = &padding6; + padding7 = &padding7; + vdo1-rdma0 = &vdo1_rdma0; + vdo1-rdma1 = &vdo1_rdma1; + vdo1-rdma2 = &vdo1_rdma2; + vdo1-rdma3 = &vdo1_rdma3; + vdo1-rdma4 = &vdo1_rdma4; + vdo1-rdma5 = &vdo1_rdma5; + vdo1-rdma6 = &vdo1_rdma6; + vdo1-rdma7 = &vdo1_rdma7; }; cpus { @@ -2532,6 +2555,16 @@ vdosys1: syscon@1c100000 { mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; + mutex1: mutex@1c101000 { + compatible = "mediatek,mt8188-disp-mutex"; + reg = <0 0x1c101000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; + interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; + }; + larb2: smi@1c102000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1c102000 0 0x1000>; @@ -2553,5 +2586,270 @@ larb3: smi@1c103000 { mediatek,larb-id = <SMI_L3_ID>; mediatek,smi = <&vpp_smi_common>; }; + + vdo1_rdma0: rdma@1c104000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; + interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; + interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; + interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; + interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; + interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: merge@1c10c000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10c000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute; + }; + + merge2: merge@1c10d000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute; + }; + + merge3: merge@1c10e000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10e000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute; + }; + + merge4: merge@1c10f000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10f000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute; + }; + + merge5: merge@1c110000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en; + }; + + ethdr0: ethdr@1c114000 { + compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; + + interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, + <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; + + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + }; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + + padding1: padding@1c11e000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11e000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING1>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; + }; + + padding2: padding@1c11f000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11f000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING2>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; + }; + + padding3: padding@1c120000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c120000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING3>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; + }; + + padding4: padding@1c121000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c121000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING4>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; + }; + + padding5: padding@1c122000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c122000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING5>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; + }; + + padding6: padding@1c123000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c123000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING6>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; + }; + + padding7: padding@1c124000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c124000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING7>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; + }; }; }; -- 2.47.0.rc1.288.g06298d1525-goog
