From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Add pinctrl device to support Amlogic A4.
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index de10e7aebf21..a748351e8b1b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -5,6 +5,7 @@
#include "amlogic-a4-common.dtsi"
#include <dt-bindings/power/amlogic,a4-pwrc.h>
+#include <dt-bindings/gpio/amlogic-a4-gpio.h>
/ {
cpus {
#address-cells = <2>;
@@ -48,3 +49,38 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ periphs_pinctrl: pinctrl@4000 {
+ compatible = "amlogic,a4-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x4000 0x0 0x02e0>;
+
+ gpio: bank@0 {
+ reg = <0x0 0x0 0x0 0x0050>,
+ <0x0 0xc0 0x0 0x0220>;
+ reg-names = "mux", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 PERIPHS_PIN_NUM>;
+ };
+ };
+
+ aobus_pinctrl: pinctrl@8e700 {
+ compatible = "amlogic,a4-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8e700 0x0 0x0064>;
+
+ ao_gpio: bank@0 {
+ reg = <0x0 0x00 0x0 0x04>,
+ <0x0 0x04 0x0 0x60>;
+ reg-names = "mux", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&aobus_pinctrl 0 0 AOBUS_PIN_NUM>;
+ };
+ };
+
+};
--
2.37.1
