Il 11/10/24 04:48, Andy-ld Lu ha scritto:
There are modified register settings for STOP_DLY_SEL and POP_EN_CNT from our next generation SoCs, due to the advanced chip manufacturing process and the resulting changes in the internal signal timing. Add two new fields to the compatibility structure to reflect the modifications. For legacy SoCs, also add the original value of 'stop_dly_sel' to the platform data, for unified code setting. Signed-off-by: Andy-ld Lu <andy-ld.lu@xxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
