> On 10/8/24 5:48 AM, Miclaus, Antoniu wrote:
> >>> +static int ad485x_get_calibscale(struct ad485x_state *st, int ch, int *val,
> int
> >> *val2)
> >>> +{
> >>> + unsigned int reg_val;
> >>> + int gain;
> >>
> >> Should be u8 gain[2] and...
> >
> > As discussed in previous patch series, the bulk operations won't work for
> these
> > chips. The CS needs to be raised between each byte read/written.
> >
>
> So the datasheet is wrong and Streaming Instruction Mode doesn't actually
> work?
>
> There is also Nonstreaming Instruction Mode if we need to read/write
> nonconsecutive
> registers without deasserting CS.
The chip was set to Nonstreaming Instruction Mode from the start in the ad485x_setup() function.
And the datasheet specifies (page 49 of 70):
"In nonstreaming instruction mode, one or more SPI transactions can be provided in
a single SPI frame."
So I guess it is an error in the datasheet.
