On Thu, 10 Oct 2024 16:27:51 +0200, Amelie Delaunay wrote: > When source data width/burst and destination data width/burst are > different, data are packed or unpacked in DMA3 channel FIFO. > Data are pushed out from DMA3 channel FIFO when the destination burst > length (= data width * burst) is reached. > If the channel is stopped before the transfer end, and if some bytes are > packed/unpacked in the DMA3 channel FIFO, these bytes are lost. > Indeed, DMA3 channel FIFO has no flush capability, only reset. > To avoid potential bytes lost, pack/unpack must be prevented by setting > memory data width/burst equal to peripheral data width/burst. > Memory accesses will be penalized. But it is the only way to avoid bytes > lost. > > Some devices (e.g. cyclic RX like UART) need this, so add the possibility > to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer > requirements' bit mask. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@xxxxxxxxxxx> > --- > Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml | 3 +++ > 1 file changed, 3 insertions(+) > Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
