On 2024/10/10 16:02, Manivannan Sadhasivam wrote: > On Mon, Oct 07, 2024 at 01:12:07PM +0900, Damien Le Moal wrote: >> The rockchip PCIe endpoint controller handles PCIe transfers addresses >> by masking the lower bits of the programmed PCI address and using the >> same number of lower bits masked from the CPU address space used for the >> mapping. For a PCI mapping of <size> bytes starting from <pci_addr>, >> the number of bits masked is the number of address bits changing in the >> address range [pci_addr..pci_addr + size - 1]. >> >> However, rockchip_pcie_prog_ep_ob_atu() calculates num_pass_bits only >> using the size of the mapping, resulting in an incorrect number of mask >> bits depending on the value of the PCI address to map. >> >> Fix this by introducing the helper function >> rockchip_pcie_ep_ob_atu_num_bits() to correctly calculate the number of >> mask bits to use to program the address translation unit. The number of >> mask bits iscalculated depending on both the PCI address and size of the >> mapping, and clamped between 8 and 20 using the macros >> ROCKCHIP_PCIE_AT_MIN_NUM_BITS and ROCKCHIP_PCIE_AT_MAX_NUM_BITS. >> > > How did you end up with these clamping values? Are the values (at least MAX > applicable to all SoCs)? > > Btw, it would be helpful if you referenced the TRM and the section that > describes the outbound mapping. I'm able to find the reference: > > Rockchip RK3399 TRM V1.3 Part2, Section 17.5.5.1.1 OK. Will add that. I really appreciate very much all the reviews you are sending, but given that this patch series depends on the series "[PATCH v4 0/7] Improve PCI memory mapping API", could we start with that one and get it queued ASAP ? Thanks ! -- Damien Le Moal Western Digital Research
