Hi Biju,
On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
>
>
>
> > -----Original Message-----
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Sent: Tuesday, October 8, 2024 6:19 PM
> > Subject: RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > > Sent: Tuesday, October 8, 2024 5:50 PM
> > > Subject: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Add OPP table for RZ/V2H(P) SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > v1->v2
> > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz
> > > ---
> > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++
> > > 1 file changed, 41 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > index 1ad5a1b6917f..4bbe75b81f54 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
> > > clock-frequency = <0>;
> > > };
> > >
> > > + /*
> > > + * The default cluster table is based on the assumption that the PLLCA55 clock
> > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
> > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
> > > + * clocked to 1.8GHz as well). The table below should be overridden in the board
> > > + * DTS based on the PLLCA55 clock frequency.
> > > + */
> > > + cluster0_opp: opp-table-0 {
> > > + compatible = "operating-points-v2";
> > > +
> > > + opp-1700000000 {
> > > + opp-hz = /bits/ 64 <1700000000>;
> > > + opp-microvolt = <900000>;
> >
> > Not sure CA-55 can change voltage from 800mV to 900mV??
> > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage.
> >
> > The manual says OD voltage is 0.9V and ND voltage is 0.8V.
> >
> > Is 1.7GHZ is ND or OD?
>
> {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V
> and for 1.1 GHz it is 0.8V.
>
> Maybe when you do /2, /4, /8 using dividers, the voltage may be still
> the same??
>
I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz the
VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect the
voltage levels at the PMIC output.
Geert, please let me know if my understanding is incorrect.
Cheers,
Prabhakar
