On Thu, Aug 22, 2024 at 5:28 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Before accessing the USB area of the RZ/G3S SoC the PWRRDY bit of the
> SYS_USB_PWRRDY register need to be cleared. When USB area is not used the
> PWRRDY bit of the SYS_USB_PWRRDY register need to be set. This register is
> in the SYSC controller address space and the assert/de-assert of the
> signal handled by SYSC_USB_PWRRDY was implemented as a reset signal.
>
> The USB modules available on the RZ/G3S SoC that need this bit set are:
> - USB ch0 (supporting host and peripheral mode)
> - USB ch2 (supporting host mode)
> - USBPHY control
>
> As the USBPHY control is the root device for all the other USB channels
> (USB ch0, USB ch1) add support to set the PWRRDY for the USB area when
> initializing the USBPHY control. As this is done though reset signals
> get the reset array in the USBPHY control driver.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
