Hi Geert,
Thank you for the review.
On Tue, Oct 8, 2024 at 11:08 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 4, 2024 at 3:31 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add OPP table for RZ/V2H(P) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
> > clock-frequency = <0>;
> > };
> >
> > + /*
> > + * The default cluster table is based on the assumption that the PLLCA55 clock
> > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
> > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
> > + * clocked to 1.8GHz as well). The table below should be overridden in the board
> > + * DTS based on the PLLCA55 clock frequency.
> > + */
> > + cluster0_opp: opp-table-0 {
> > + compatible = "operating-points-v2";
> > +
> > + opp-1700000000 {
> > + opp-hz = /bits/ 64 <1700000000>;
> > + opp-microvolt = <900000>;
> > + clock-latency-ns = <300000>;
> > + };
> > + opp-850000000 {
> > + opp-hz = /bits/ 64 <850000000>;
> > + opp-microvolt = <900000>;
>
> According to Table 10.1-2 ("Recommended Operating Range"), this should
> be 800000 for this and all operating points below.
>
Agreed, I had missed that. I added the voltage level based on the
schematic VDD09_CA55
Cheers,
Prabhakar
