On 23/03/15 16:56, Mark Brown wrote:
On Mon, Mar 23, 2015 at 11:00:53AM +0000, Peter Rosin wrote:
Strongly agreed that we should fix this before it is published (I assumed
that is was included in 3.19, it felt so long ago that Mark merged it...). My
preference would be to remove the pll-lock things entirely though. Assuming
you don't need it for your board of course, but I doubt it from your description.
I used it to make sure I had understood the chip correctly, that's all.
It didn't make v3.19 so if we're very quick we can get this in as a fix.
Can someone resend a version which splits this into two patches, one
deleting the existing code to configure GPIO 4 and the other adding the
configurability? I can then send the removal as a bug fix to v4.0 so we
don't have any compatibility issues and add the new feature for v4.1.
Ok, will do, although it seems that both Peter and I agree that the
configurability is not required, so I'll just submit a patch for the
deletion.
- Howard
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