On Fri, Oct 04, 2024 at 04:05:55PM +0800, Inochi Amaoto wrote: > Sophgo SG2044 has a new version of T-HEAD C920, which implement > a fully featured ACLINT device. This ACLINT has an extra SSWI > field to support fast S-mode IPI. > > Add necessary compatible string for the T-HEAD ACLINT sswi device. > > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx> > --- > .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > new file mode 100644 > index 000000000000..0106fbf3ea1f > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device > + > +maintainers: > + - Inochi Amaoto <inochiama@xxxxxxxxxxx> > + > +description: > + The SSWI device is a part of the riscv ACLINT device. It provides > + supervisor-level IPI functionality for a set of HARTs on a RISC-V > + platform. It provides a register to set an IPI (SETSSIP) for each > + HART connected to the SSWI device. If it is part of the aclint, why should it have a separate node, rather than be part of the existing aclint node as a third reg property?
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