On Thu, Oct 03, 2024 at 11:20:03PM +0530, Kiran Kumar C.S.K wrote: > >> +---------+ > >> | 48MHZ | > >> +----+----+ > >> |(clock) > >> v > >> +----+----+ > >> +------| CMN PLL | > >> | +----+----+ > >> | |(clock) > >> | v > >> | +----+----+ +----+----+ clock +----+----+ > >> | +---| NSSCC | | GCC |--------->| MDIO | > >> | | +----+----+ +----+----+ +----+----+ > >> | | |(clock & reset) |(clock & reset) > >> | | v v > >> | | +-----------------------------+----------+----------+---------+ > >> | | | +-----+ |EDMA FIFO | | EIP FIFO| > >> | | | | SCH | +----------+ +---------+ > >> | | | +-----+ | | | > >> | | | +------+ +------+ +-------------------+ | > >> | | | | BM | | QM | | L2/L3 Switch Core | | > >> | | | +------+ +------+ +-------------------+ | > >> | | | | | > >> | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | > >> | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | > >> | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | > >> | | | | | | | | | | > >> | | +-----+---------+---------+---------+---------+---------+-----+ > >> | | | | | | | | > >> | | +---+---------+---------+---------+---+ +---+---+ +---+---+ > >> +--+---->| PCS0 | | PCS1 | | PCS2 | > >> | clock +---+---------+---------+---------+---+ +---+---+ +---+---+ > >> | | | | | | | > >> | +---+---------+---------+---------+---+ +---+---+ +---+---+ > >> | clock +----------------+ | | | | | > >> +------->|Clock Controller| 4-port Eth PHY | | PHY4 | | PHY5 | > >> +----------------+--------------------+ +-------+ +-------+ ... > >> 3) PCS driver patch series: > >> Driver for the PCS block in IPQ9574. New IPQ PCS driver will > >> be enabled in drivers/net/pcs/ > >> Dependent on NSS CC patch series (2). > > > > I assume this dependency is pure at runtime? So the code will build > > without the NSS CC patch series? > > The MII Rx/Tx clocks are supplied from the NSS clock controller to the > PCS's MII channels. To represent this in the DTS, the PCS node in the > DTS is configured with the MII Rx/Tx clock that it consumes, using > macros for clocks which are exported from the NSS CC driver in a header > file. So, there will be a compile-time dependency for the dtbindings/DTS > on the NSS CC patch series. We will clearly call out this dependency in > the cover letter of the PCS driver. Hope that this approach is ok. Please distinguish between the clocks that are part of the connection between the PCS and PHY and additional clocks. For example, RGMII has its own clocks that are part of the RGMII interface. Despite DT having a way to describe clocks, these clocks are fundamental to the RGMII interface and are outside of the scope of DT to describe. Their description is implicit in the relationship between the PHY and network driver. Also, the PCS itself is a subset of the network driver, and we do not (as far as I know) ever describe any kind of connection between a PCS and PHY. That would be madness when we have situations where the PHY can change its serdes mode, causing the MAC to switch between several PCS - which PCS would one associate the PHY with in DT when the "mux" is embedded in the ethernet driver and may be effectively transparent? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
