On 4.10.2024 11:06 AM, Abel Vesa wrote: > The PCIe 6a controller and PHY can be configured in 4-lanes mode or > 2-lanes mode. For 4-lanes mode, it fetches the lanes provided by PCIe 6b. > For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 > lanes. Configure it in 4-lane mode and then each board can configure it > depending on the design. Both the QCP and CRD boards, currently upstream, > use PCIe 6a for NVMe in 4-lane mode. Mark the controller as 4-lane as > well. This is the last change needed in order to support NVMe with Gen4 > 4-lanes on all existing X Elite boards. > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > --- > Changes in v2: > - Re-worded the commit message according to Johan's suggestions > - Dropped the clocks changes. > - Dropped the fixes tag as this relies on the Gen4 4-lanes stability > patchset which has been only merged in 6.12, so backporting this patch > would break NVMe support for all platforms. > - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@xxxxxxxxxx > --- Depends on https://lore.kernel.org/linux-arm-msm/20240916082307.29393-3-johan+linaro@xxxxxxxxxx/ Otherwise Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> Konrad
