From: Devi Priya <quic_devipriy@xxxxxxxxxxx> Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@xxxxxxxxxxx> --- Changes in V6: - Remove bias_pll_cc_clk, bias_pll_nss_noc_clk, bias_pll_ubi_nc_clk nodes from DTS. Because these clocks will be enabled by CMN PLL [1]. Until the CMN PLL driver posted with these clocks set these entries to 0 in the nsscc node. 1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@xxxxxxxxxxx/ - Fixed the title arch/arm64/boot/dts/qcom/ipq9574.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 08a82a5cf667..943c5757c36e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,8 @@ #include <dt-bindings/interconnect/qcom,ipq9574.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> #include <dt-bindings/thermal/thermal.h> / { @@ -756,6 +758,27 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <0>, + <0>, + <0>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + #interconnect-cells = <1>; + }; }; thermal-zones { -- 2.34.1
