On 6/26/2024 11:43 PM, Dmitry Baryshkov wrote:
> On Wed, Jun 26, 2024 at 08:03:01PM GMT, Devi Priya wrote:
>> Add a node for the nss clock controller found on ipq9574 based devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
>> ---
>> Changes in V5:
>> - Dropped interconnects from nsscc node and added
>> interconnect-cells to NSS clock provider so that it can be used
>> as icc provider.
>>
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++
>> 1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 48dfafea46a7..b6f8800bf63c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -11,6 +11,8 @@
>> #include <dt-bindings/interconnect/qcom,ipq9574.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> #include <dt-bindings/thermal/thermal.h>
>>
>> / {
>> @@ -19,6 +21,24 @@ / {
>> #size-cells = <2>;
>>
>> clocks {
>> + bias_pll_cc_clk: bias-pll-cc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <1200000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <461500000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <353000000>;
>> + #clock-cells = <0>;
>> + };
>
> What is the source for these clocks? Is it really an on-board crystal?
>
Hi Dmitry,
Sorry for the delayed response.
No, the CMN PLL [1] is the source for these clocks. Will remove these
nodes and set these entries to 0 in the nsscc node until the CMN
PLL driver posted with these clocks.
1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@xxxxxxxxxxx/
Thanks & Regards,
Manikanta.
