On Thu, Oct 03, 2024 at 09:49:51AM +0200, Clément Léger wrote:
>
>
> On 02/10/2024 18:10, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> >
> > Using Clement's new validation callbacks, support checking that
> > dependencies have been satisfied for the floating point extensions.
> >
> > The check for "d" might be slightly confusingly shorter than that of "f",
> > despite "d" depending on "f". This is because the requirement that a
> > hart supporting double precision must also support single precision,
> > should be validated by dt-bindings etc, not the kernel but lack of
> > support for single precision only is a limitation of the kernel.
> >
> > Since vector will now be disabled proactively, there's no need to clear
> > the bit in elf_hwcap in riscv_fill_hwcap() any longer.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > ---
> > arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++-----------
> > 1 file changed, 25 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 84a2ad2581cb0..b8a22ee76c2ef 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -101,6 +101,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
> > return 0;
> > }
> >
> > +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
> > + const unsigned long *isa_bitmap)
> > +{
> > + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
> > + pr_warn_once("This kernel does not support systems with F but not D\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (IS_ENABLED(CONFIG_FPU))
> > + return -EINVAL;
>
> Shouldn't this be !IS_ENABLED(CONFIG_FPU)) ? I mean, if the f extension
> is enabled but not CONFIG_FPU, then disable it.
Of course. I wonder how my userspace didn't blow up.
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