On Wed, Oct 02, 2024 at 05:10:57PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > Section 33.18.2. Zve*: Vector Extensions for Embedded Processors > in [1] says: > | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends > | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension > > | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend > | upon the F extension > > | The Zve64d extension depends upon the D extension > > Apply these rules to the bindings to help prevent invalid combinations. > > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1] > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
