From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
While the auxiliary bus was a nice bandaid, and meant that re-writing
the representation of the clock regions in devicetree was not required,
it has run its course. The "mss_top_sysreg" region that contains the
clock and reset regions, also contains pinctrl and an interrupt
controller, so the time has come rewrite the devicetree and probe the
reset controller from an mfd devicetree node, rather than implement
those drivers using the auxiliary bus. Wanting to avoid propagating this
naive/incorrect description of the hardware to the new pic64gx SoC is a
major motivating factor here.
Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
drivers/reset/reset-mpfs.c | 83 ++++++++++++++++++++++++++++++++------
1 file changed, 71 insertions(+), 12 deletions(-)
diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c
index 710f9c1676f93..ac72e0fc405ed 100644
--- a/drivers/reset/reset-mpfs.c
+++ b/drivers/reset/reset-mpfs.c
@@ -9,10 +9,12 @@
#include <linux/auxiliary_bus.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/microchip,mpfs-clock.h>
#include <soc/microchip/mpfs.h>
@@ -27,14 +29,37 @@
#define MPFS_SLEEP_MIN_US 100
#define MPFS_SLEEP_MAX_US 200
+#define REG_SUBBLK_RESET_CR 0x88u
+
/* block concurrent access to the soft reset register */
static DEFINE_SPINLOCK(mpfs_reset_lock);
struct mpfs_reset {
void __iomem *base;
+ struct regmap *regmap;
struct reset_controller_dev rcdev;
};
+static inline u32 mpfs_reset_read(struct mpfs_reset *rst)
+{
+ u32 ret;
+
+ if (rst->regmap)
+ regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, &ret);
+ else
+ ret = readl(rst->base);
+
+ return ret;
+}
+
+static inline void mpfs_reset_write(struct mpfs_reset *rst, u32 val)
+{
+ if (rst->regmap)
+ regmap_write(rst->regmap, REG_SUBBLK_RESET_CR, val);
+ else
+ writel(val, rst->base);
+}
+
static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct mpfs_reset, rcdev);
@@ -51,9 +76,9 @@ static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
spin_lock_irqsave(&mpfs_reset_lock, flags);
- reg = readl(rst->base);
+ reg = mpfs_reset_read(rst);
reg |= BIT(id);
- writel(reg, rst->base);
+ mpfs_reset_write(rst, reg);
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
@@ -68,9 +93,9 @@ static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
spin_lock_irqsave(&mpfs_reset_lock, flags);
- reg = readl(rst->base);
+ reg = mpfs_reset_read(rst);
reg &= ~BIT(id);
- writel(reg, rst->base);
+ mpfs_reset_write(rst, reg);
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
@@ -80,7 +105,7 @@ static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
{
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
- u32 reg = readl(rst->base);
+ u32 reg = mpfs_reset_read(rst);
/*
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
@@ -130,11 +155,45 @@ static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
return index - MPFS_PERIPH_OFFSET;
}
-static int mpfs_reset_probe(struct auxiliary_device *adev,
- const struct auxiliary_device_id *id)
+static int mpfs_reset_mfd_probe(struct platform_device *pdev)
{
- struct device *dev = &adev->dev;
struct reset_controller_dev *rcdev;
+ struct device *dev = &pdev->dev;
+ struct mpfs_reset *rst;
+
+ rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
+ if (!rst)
+ return -ENOMEM;
+
+ rcdev = &rst->rcdev;
+ rcdev->dev = dev;
+ rcdev->ops = &mpfs_reset_ops;
+
+ rcdev->of_node = pdev->dev.parent->of_node;
+ rcdev->of_reset_n_cells = 1;
+ rcdev->of_xlate = mpfs_reset_xlate;
+ rcdev->nr_resets = MPFS_NUM_RESETS;
+
+ rst->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
+ if (IS_ERR(rst->regmap))
+ dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n");
+
+ return devm_reset_controller_register(dev, rcdev);
+}
+
+static struct platform_driver mpfs_reset_mfd_driver = {
+ .probe = mpfs_reset_mfd_probe,
+ .driver = {
+ .name = "mpfs-reset",
+ },
+};
+module_platform_driver(mpfs_reset_mfd_driver);
+
+static int mpfs_reset_adev_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct reset_controller_dev *rcdev;
+ struct device *dev = &adev->dev;
struct mpfs_reset *rst;
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
@@ -145,8 +204,8 @@ static int mpfs_reset_probe(struct auxiliary_device *adev,
rcdev = &rst->rcdev;
rcdev->dev = dev;
- rcdev->dev->parent = dev->parent;
rcdev->ops = &mpfs_reset_ops;
+
rcdev->of_node = dev->parent->of_node;
rcdev->of_reset_n_cells = 1;
rcdev->of_xlate = mpfs_reset_xlate;
@@ -222,12 +281,12 @@ static const struct auxiliary_device_id mpfs_reset_ids[] = {
};
MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
-static struct auxiliary_driver mpfs_reset_driver = {
- .probe = mpfs_reset_probe,
+static struct auxiliary_driver mpfs_reset_aux_driver = {
+ .probe = mpfs_reset_adev_probe,
.id_table = mpfs_reset_ids,
};
-module_auxiliary_driver(mpfs_reset_driver);
+module_auxiliary_driver(mpfs_reset_aux_driver);
MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
MODULE_AUTHOR("Conor Dooley <conor.dooley@xxxxxxxxxxxxx>");
--
2.45.2
