On Wed, Oct 02, 2024 at 12:07:06PM +0200, Heiko Stübner wrote: > Am Mittwoch, 2. Oktober 2024, 11:54:14 CEST schrieb Yao Zi: > > On Wed, Oct 02, 2024 at 08:31:53AM +0200, Krzysztof Kozlowski wrote: > > > On Tue, Oct 01, 2024 at 04:23:56AM +0000, Yao Zi wrote: > > > > +/* > > > > + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. > > > > + * Copyright (c) 2024 Yao Zi <ziyao@xxxxxxxxxxx> > > > > + * Author: Joseph Chen <chenjh@xxxxxxxxxxxxxx> > > > > + */ > > > > + > > > > +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H > > > > +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H > > > > + > > > > +// CRU_SOFTRST_CON03 (Offset: 0xA0C) > > > > +#define SRST_CORE0_PO 0x00000030 > > > > +#define SRST_CORE1_PO 0x00000031 > > > > +#define SRST_CORE2_PO 0x00000032 > > > > +#define SRST_CORE3_PO 0x00000033 > > > > +#define SRST_CORE0 0x00000034 > > > > +#define SRST_CORE1 0x00000035 > > > > +#define SRST_CORE2 0x00000036 > > > > +#define SRST_CORE3 0x00000037 > > > > +#define SRST_NL2 0x00000038 > > > > +#define SRST_CORE_BIU 0x00000039 > > > > +#define SRST_CORE_CRYPTO 0x0000003A > > > > + > > > > +// CRU_SOFTRST_CON05 (Offset: 0xA14) > > > > +#define SRST_P_DBG 0x0000005D > > > > +#define SRST_POT_DBG 0x0000005E > > > > +#define SRST_NT_DBG 0x0000005F > > > > > > What are all these? Registers? Not a binding. > > > > > > Binding constants are numerical values from 0, incremented by one, > > > > Do we have related documentation about this, or I just miss it? > > here the value notation in hex format is very strange. > > For reference have a look at the rk3576 and rk3588, which follow the style > recommendations. I have checked their implementation before sending the reply. Older Rockchip reset bindings, including this series, encoding register offsets and effective bits in IDs, resulting in the mess. In next revision, the new style will be adapted, just like rk3576/3588. But what I'm asking for is a generic style doc of writing dt-binding headers :) Cheers, Yao Zi
