On Fri, Sep 13, 2024 at 3:04 AM Taewan Kim <trunixs.kim@xxxxxxxxxxx> wrote:
>
> From: Byoungtae Cho <bt.cho@xxxxxxxxxxx>
>
> Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> is almost similar to ExynosAutoV9, but some CPU configurations are quite
> different, so it should be added. Plus it also support DBGACK like as
> GS101 SoC.
>
> Signed-off-by: Byoungtae Cho <bt.cho@xxxxxxxxxxx>
> Signed-off-by: Taewan Kim <trunixs.kim@xxxxxxxxxxx>
> ---
> drivers/watchdog/s3c2410_wdt.c | 37 +++++++++++++++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 686cf544d0ae..c25133348f0e 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -63,6 +63,10 @@
> #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT 0x1420
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN 0x1444
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT 0x1720
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN 0x1744
>
> #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> QUIRK_HAS_DBGACK_BIT,
> };
>
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> + .mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> + .cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_DBGACK_BIT,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> + .mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> + .cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_DBGACK_BIT,
> +};
> +
> static const struct of_device_id s3c2410_wdt_match[] = {
> { .compatible = "google,gs101-wdt",
> .data = &drv_data_gs101_cl0 },
> @@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> .data = &drv_data_exynos850_cl0 },
> { .compatible = "samsung,exynosautov9-wdt",
> .data = &drv_data_exynosautov9_cl0 },
> + { .compatible = "samsung,exynosautov920-wdt",
> + .data = &drv_data_exynosautov920_cl0},
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -643,7 +675,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> if (variant == &drv_data_exynos850_cl0 ||
> variant == &drv_data_exynosautov9_cl0 ||
> - variant == &drv_data_gs101_cl0) {
> + variant == &drv_data_gs101_cl0 ||
> + variant == &drv_data_exynosautov920_cl0) {
> u32 index;
> int err;
>
> @@ -662,6 +695,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> variant = &drv_data_exynosautov9_cl1;
> else if (variant == &drv_data_gs101_cl0)
> variant = &drv_data_gs101_cl1;
> + else if (variant == &drv_data_exynosautov920_cl1)
Shouldn't it be cl0 here?
> + variant = &drv_data_exynosautov920_cl1;
> break;
> default:
> return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> --
> 2.46.0
>
>
