On Thu, 26 Sep 2024 12:29:13 +0200, Dragan Simic wrote:
> Move the "l3_cache" node outside the "cpus" node in the base dtsi file for
> Rockchip RK3588(S) SoCs. The A55 and A76 CPU cores in these SoCs belong to
> the ARM DynamIQ IP core lineup, which places the L3 cache outside the CPUs
> and into the DynamIQ Shared Unit (DSU). [1] Thus, moving the L3 cache DT
> node one level higher in the DT improves the way the physical topology of
> the RK3588(S) SoCs is represented in the SoC dtsi files.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Move L3 cache outside CPUs in RK3588(S) SoC dtsi
commit: df5f6f2f62b9b50cef78f32909485b00fc7cf7f2
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
