Introduces the Device Tree for the QCS615 platform. Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - QFPROM - TLMM - Watchdog - RPMH controller - Sleep stats driver - Rpmhpd power controller - Interconnect - GCC and Rpmhcc - QUP with Uart serial support Bindings and base Device Tree for the QCS615 SoC are splited in four parts: - 1-3: Binding files for QCS615 SoC and PDC (Reviewed) - 4 : Soc table entry (Reviewed) - 5-6: Initial DTSI and RIDE board device tree - 7 : Enable uart related configs Bindings Dependencies: - watchdog: https://lore.kernel.org/all/20240920-add_watchdog_compatible_for_qcs615-v2-1-427944f1151e@xxxxxxxxxxx/ - Reviewed - qfprom: https://lore.kernel.org/all/20240912-add_qfprom_compatible_for_qcs615-v1-1-9ef2e26c14ee@xxxxxxxxxxx/ - Reviewed - tcsr: https://lore.kernel.org/all/20240920-add_tcsr_compatible_for_qcs615-v2-1-8ce2dbc7f72c@xxxxxxxxxxx/ - Reviewed - tlmm: https://lore.kernel.org/all/20240920-add_qcs615_pinctrl_driver-v2-1-e03c42a9d055@xxxxxxxxxxx/ - Reviewed - interconnect: https://lore.kernel.org/all/20240924143958.25-2-quic_rlaggysh@xxxxxxxxxxx/ - Reviewed - rpmhcc: https://lore.kernel.org/all/20240920-qcs615-clock-driver-v2-1-2f6de44eb2aa@xxxxxxxxxxx/ - Reviewed - gcc: https://lore.kernel.org/all/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@xxxxxxxxxxx/ - Reviewed - rpmhpd: https://lore.kernel.org/all/20240920-add_qcs615_powerdomains_driver_support-v1-1-8846efaf9454@xxxxxxxxxxx/ - Reviewed Build Dependencies: - tlmm: https://lore.kernel.org/all/20240920-add_qcs615_pinctrl_driver-v2-2-e03c42a9d055@xxxxxxxxxxx/ - gcc: https://lore.kernel.org/all/20240920-qcs615-clock-driver-v2-4-2f6de44eb2aa@xxxxxxxxxxx/ Patch made the following verifications: - Successfully passed dt_binding_check with DT_CHECKER_FLAGS=-m for earch binding file - Successfully passed dtbs_check with W=1 for dts - Verified CPU Hotplug, idle and online CPUs on QCS615 ride board - Checked pinctrl-maps path - Verified watchdog functionality with "echo 1 > /dev/watchdog", can trigger a watchdog bark and later bite - Verified functionality with UART console on QCS615 ride board - RPMH controller driver probed successfully - Sleep stats driver probed successfully and checked qcom_stats node on QCS615 ride board Signed-off-by: Lijuan Gao <quic_lijuang@xxxxxxxxxxx> --- Changes in v3: - Added interconnect, GCC, RPMHCC, QPU, and RPMHPD related nodes for UART console - Enabled UART condole on ride board device - Link to v2: https://lore.kernel.org/r/20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@xxxxxxxxxxx Changes in v2: - Collected reviewed-bys - Removed extra blank line - Removed redundant function - Renamed xo-board to xo-board-clk and move it and sleep-clk to board dts - Renamed system-sleep to cluster_sleep_2 - Removed cluster1 - Added entry-method for idle-states - Added DTS chassis type - Added TCSR Clock Controllers - Added Reserved Shared memory - Added QFPROM - Added TLMM - Added Watchdog - Added RPMH controller - Added Sleep stats driver - Link to v1: https://lore.kernel.org/r/20240828-add_initial_support_for_qcs615-v1-0-5599869ea10f@xxxxxxxxxxx --- --- Lijuan Gao (7): dt-bindings: arm: qcom: document QCS615 and the reference board dt-bindings: arm: qcom,ids: add SoC ID for QCS615 dt-bindings: qcom,pdc: document QCS615 Power Domain Controller soc: qcom: socinfo: Add QCS615 SoC ID table entry arm64: dts: qcom: add initial support for QCS615 DTSI arm64: dts: qcom: add base QCS615 RIDE dts arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615 Documentation/devicetree/bindings/arm/qcom.yaml | 6 + .../bindings/interrupt-controller/qcom,pdc.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 222 +++++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 688 +++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + drivers/soc/qcom/socinfo.c | 1 + include/dt-bindings/arm/qcom,ids.h | 1 + 8 files changed, 923 insertions(+) --- base-commit: c83f0b825741bcb9d8a7be67c63f6b9045d30f5a change-id: 20240924-add_initial_support_for_qcs615-a01bb2dd4650 prerequisite-change-id: 20240919-qcs615-clock-driver-d74abed69854:v2 prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91 prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f prerequisite-patch-id: 88c7ce656ce89a6505e27699c762311a7a7e5411 prerequisite-change-id: 20240920-add_qcs615_powerdomains_driver_support-c934be5c56fb:v1 prerequisite-patch-id: 834bcb01579ed7fa9489e705b2645853c6371767 prerequisite-patch-id: e838c8ea2b67839cf427833738c200fa149d5634 prerequisite-change-id: 20240920-add_qcs615_pinctrl_driver-f6aa6352a4ae:v2 prerequisite-patch-id: 8486c6329ab9b8d9cf78b4ef1ceaa8abfd62be3e prerequisite-patch-id: a0f1c46b6aaa39ae5e579895bf6ba334c8d65840 prerequisite-change-id: 20240920-add_tcsr_compatible_for_qcs615-091aa67f1c6f:v2 prerequisite-patch-id: 131af7e3b2e66243b10e0de2193cfa3a2fe5971d prerequisite-change-id: 20240920-add_watchdog_compatible_for_qcs615-eec8a8c2c924:v2 prerequisite-patch-id: 3a76212d3a3e930d771312ff9349f87aee5c55d5 prerequisite-change-id: 20240911-add_qfprom_compatible_for_qcs615-e3b02f6fa71e:v1 prerequisite-patch-id: 8a2454d5e07e56a6dd03f762f498051065635d85 Best regards, -- Lijuan Gao <quic_lijuang@xxxxxxxxxxx>
