On Fri, Sep 20, 2024 at 06:41:07PM +0300, Igor Prusov wrote:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + clock-names:
> + items:
> + - const: sclk
> + - const: lrclk
This is quite weird and doesn't seem to correspond to the chip datasheet
at:
http://www.everest-semi.com/pdf/ES7243%20PB.pdf
https://www.pawpaw.cn/media/documents/2022-04/ES7243E_DS_pawpaw%E6%9C%A8%E7%93%9C%E7%A7%91%E6%8A%80.pdf
The SCLK and LRCLK appear to be the bit and frame sync clocks which
would not normally be exposed directly via the clock API (so this is
probably not going to be joined up with whatever SoC it's connected to).
On the other hand there *is* a MCLK which would much more normally be
represented in the DT bindings and isn't represented here or managed by
the driver.
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