On Sat, Sep 21, 2024 at 10:58:46PM +0100, Conor Dooley wrote: > On Fri, Sep 20, 2024 at 03:40:31PM +0200, Krzysztof Kozlowski wrote: > > On 20/09/2024 15:33, Andrei Stefanescu wrote: > > > Hi Conor, > > > > > > Thank you for your review! > > > > > > On 20/09/2024 15:46, Conor Dooley wrote: > > >> On Thu, Sep 19, 2024 at 04:47:22PM +0300, Andrei Stefanescu wrote: > > >>> Add support for the GPIO driver of the NXP S32G2/S32G3 SoCs. > > >>> > > >>> Signed-off-by: Phu Luu An <phu.luuan@xxxxxxx> > > >>> Signed-off-by: Larisa Grigore <larisa.grigore@xxxxxxx> > > >>> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@xxxxxxx> > > >>> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@xxxxxxxxxxx> > > >>> --- > > >>> .../bindings/gpio/nxp,s32g2-siul2-gpio.yaml | 107 ++++++++++++++++++ > > >>> 1 file changed, 107 insertions(+) > > >>> create mode 100644 Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml > > >>> > > >>> diff --git a/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml > > >>> new file mode 100644 > > >>> index 000000000000..0548028e6745 > > >>> --- /dev/null > > >>> +++ b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml > > >>> @@ -0,0 +1,107 @@ > > >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause > > >>> +# Copyright 2024 NXP > > >>> +%YAML 1.2 > > >>> +--- > > >>> +$id: http://devicetree.org/schemas/gpio/nxp,s32g2-siul2-gpio.yaml# > > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > > >>> + > > >>> +title: NXP S32G2 SIUL2 GPIO controller > > >>> + > > >>> +maintainers: > > >>> + - Ghennadi Procopciuc <Ghennadi.Procopciuc@xxxxxxx> > > >>> + - Larisa Grigore <larisa.grigore@xxxxxxx> > > >>> + - Andrei Stefanescu <andrei.stefanescu@xxxxxxxxxxx> > > >>> + > > >>> +description: > > >>> + Support for the SIUL2 GPIOs found on the S32G2 and S32G3 > > >>> + chips. It includes an IRQ controller for all pins which have > > >>> + an EIRQ associated. > > >>> + > > >>> +properties: > > >>> + compatible: > > >>> + items: > > >>> + - const: nxp,s32g2-siul2-gpio > > >> > > >> Commit message and binding description say s32g2 and s32g3, but there's > > >> only a compatible here for g2. > > > > > > Yes, the SIUL2 GPIO hardware is the same for both S32G2 and S32G3 SoCs. I plan > > > to reuse the same compatible when I add the SIUL2 GPIO device tree node for > > > the S32G3 boards. Would that be ok? > > > > There are only few exceptions where re-using compatible is allowed. Was > > S32G on them? Please consult existing practice/maintainers and past reviews. Just in case this was not clear - comment "please consult existing..." was towards Andrei, not you Conor. > > Pretty sure I had a similar conversation about another peripheral on > these devices, and it was established that these are not different fusings > etc, but rather are independent SoCs that reuse an IP core. Given that, > I'd expect to see a fallback compatible used here, as is the norm. Yep. Best regards, Krzysztof
