On 22/09/2024 08:13, Thippeswamy Havalige wrote: > The Xilinx Versal premium series has CPM5 block which supports two typeA > Root Port controller functionality at Gen5 speed. > > Add compatible string to distinguish between two CPM5 rootport controller1. > since Legacy and error interrupt register and bits for both the controllers > are at different offsets. > > Signed-off-by: Thippeswamy Havalige <thippesw@xxxxxxx> Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Best regards, Krzysztof
