From: Angelo Dureghello <adureghello@xxxxxxxxxxxx>
There is a version AXI DAC IP block (for FPGAs) that provides
a physical bus for AD3552R and similar chips, and acts as
an SPI controller.
For this case, the binding is modified to include some
additional properties.
Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx>
---
.../devicetree/bindings/iio/dac/adi,ad3552r.yaml | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
index 41fe00034742..aca4a41c2633 100644
--- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
@@ -60,6 +60,18 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
+ io-backends:
+ description: The iio backend reference.
+ An example backend can be found at
+ https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html
+ maxItems: 1
+
+ adi,synchronous-mode:
+ description: Enable waiting for external synchronization signal.
+ Some AXI IP configuration can implement a dual-IP layout, with internal
+ wirings for streaming synchronization.
+ type: boolean
+
'#address-cells':
const: 1
@@ -128,6 +140,7 @@ patternProperties:
- custom-output-range-config
allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
properties:
compatible:
@@ -238,4 +251,33 @@ examples:
};
};
};
+
+ - |
+ axi_dac: spi@44a70000 {
+ compatible = "adi,axi-ad3552r";
+ reg = <0x44a70000 0x1000>;
+ dmas = <&dac_tx_dma 0>;
+ dma-names = "tx";
+ #io-backend-cells = <0>;
+ clocks = <&ref_clk>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "adi,ad3552r";
+ reg = <0>;
+ reset-gpios = <&gpio0 92 0>;
+ io-backends = <&axi_dac>;
+ spi-max-frequency = <66000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ adi,output-range-microvolt = <(-10000000) (10000000)>;
+ };
+ };
+ };
...
--
2.45.0.rc1
