> > Performing a dummy read ensures that the register write operation is fully > > completed, mitigating any potential bus delays that could otherwise impact > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > However, this can lead to rapid toggling of the GPIO because the write > > operation is POSTed and does not wait for a bus acknowledgment. > > > > Signed-off-by: Billy Tsai <billy_tsai@xxxxxxxxxxxxxx> > ... are you aware of any other driver concerns of a similar nature wrt > the architecture of the SoCs? No, we are only aware of this issue with the GPIO controller, which affects the output pin behavior immediately after register write.
