Hi Hyungwon, On 19 March 2015 at 01:02, Hyungwon Hwang <human.hwang@xxxxxxxxxxx> wrote: >> > + /* >> > + * The input PLL clock for MIPI DSI in Exynos5433 seems to >> > be fixed >> > + * by OSC CLK. >> > + */ >> > + fin = 24 * MHZ; >> >> Er, is this always true on other platforms as well? Shouldn't this be >> a part of the DeviceTree description? > > I forgot to change the comment in development. Finally it is found that > all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I will remove > the comment, but remain the code as it is. Fair enough. Should pll_clk be removed from the DT description then, if it's fixed to the oscillator? > Thanks for your review. I will send it again with the changes you > suggested. Thanks very much! Cheers, Daniel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
