Xilinx clocking wizard IP core's dynamic reconfiguration support is
optionally enabled at build time. Add a devicetree boolean property to
describe whether the hardware supports this feature or not.
Since dynamic reconfiguration support was previously assumed enabled,
introduce a property to indicate the inverse, in order to maintain
devicetree backwards compatibility. Hence, this new xlnx,static-config
property should be specified when dynamic reconfiguration support is
disabled in the IP core configuration.
Signed-off-by: Harry Austen <hpausten@xxxxxxxxxxxxxx>
---
v1 -> v2:
- Invert meaning of the new DT property
- Renamed from xlnx,dynamic-reconfig to xlnx,static-config
.../devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
index 9d5324dc1027a..b44a76a958f4e 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
@@ -39,6 +39,11 @@ properties:
- const: clk_in1
- const: s_axi_aclk
+ xlnx,static-config:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate whether the core has been configured without support for dynamic
+ runtime reconfguration of the clocking primitive MMCM/PLL.
xlnx,speed-grade:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -70,6 +75,7 @@ examples:
compatible = "xlnx,clocking-wizard";
reg = <0xb0000000 0x10000>;
#clock-cells = <1>;
+ xlnx,static-config;
xlnx,speed-grade = <1>;
xlnx,nr-outputs = <6>;
clock-names = "clk_in1", "s_axi_aclk";
--
2.46.0
