On 9/9/24 9:38 PM, Frank Li wrote:
[...]
+ * Use __raw_writel() to minimize the interval between two writes to
+ * the SAR register to increase the fastest pwm frequency supported.
+ *
+ * When the PWM period is longer than 2us(or <500KHz), this workaround
+ * can solve this problem. No software workaround is available If PMW
PWM , typo
+ * period is shorter than IO write.
+ */
+ c = clkrate * 1500;
+ do_div(c, NSEC_PER_SEC);
+
+ local_irq_save(flags);
+ val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));
+ if (duty_cycles < imx->duty_cycle && val < MX3_PWMSR_FIFOAV_2WORDS) {
+ val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);
+ if ((val + c >= duty_cycles && val < imx->duty_cycle) ||
+ /*
+ * If counter is close to period, controller may roll over
+ * when next IO write.
+ */
+ val + c >= period_cycles)
+ writel_relaxed(imx->duty_cycle, reg_sar);
Maybe use imx->mmio_base + MX3_PWMSAR instead of reg_sar here, to be
consistent with imx->mmio_base + MX3_PWMSR above ?
+ }
+ writel_relaxed(duty_cycles, reg_sar);
Same here
+ local_irq_restore(flags);
+
writel(period_cycles, imx->mmio_base + MX3_PWMPR);
[...]
Looks good otherwise, thanks !
