On Sat, Aug 31, 2024 at 08:45:06AM +0200, Krzysztof Kozlowski wrote: > On Fri, Aug 30, 2024 at 05:00:40PM +0100, Conor Dooley wrote: > > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > > > This is a pretty rough document I conjured up in 5 minutes, to document > > my expectations for compatible strings for both our FPGA IP blocks and > > reference designs that we ship, a la the one that exists for SiFive IPs. > > There's been some internal conversations lately about this naming etc, > > so good to have something written down. > > > > You can try to make it a schema. Take a peak at: > Documentation/devicetree/bindings/arm/qcom-soc.yaml Sure, I don't mind doing that - however given the breadth of microchip's portfolio (and thus naming schemes) there may actually be little by way of enforcement gained by making it into a binding. I'll give it a go and see how permissive it ends up having to be.
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