On Thu, 05 Sep 2024 17:17:31 +0200
Angelo Dureghello <adureghello@xxxxxxxxxxxx> wrote:
> From: Angelo Dureghello <adureghello@xxxxxxxxxxxx>
>
> There is a version AXI DAC IP block (for FPGAs) that provides
> a physical bus for AD3552R and similar chips. This can be used
> instead of a typical SPI controller to be able to use the chip
> in ways that typical SPI controllers are not capable of.
>
> The binding is modified so that either the device is a SPI
> peripheral or it uses an io-backend.
>
> Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx>
>
> required:
> - compatible
> - - reg
> - - spi-max-frequency
Sort of feels like both reg and spi-max-frequency
are valid things to specify.
Maybe we have an excellent IP and dodgy wiring so want
to clamp the frequency (long term - don't need to support
in the driver today).
Maybe we have an axi_dac IP that supports multiple
front end devices? So maybe just keep reg?
>
> additionalProperties: false
>
> @@ -238,4 +254,26 @@ examples:
> };
> };
> };
> +
> + - |
> + backend: axi_dac@44a70000 {
> + compatible = "adi,axi-dac-ad3552r";
> + reg = <0x44a70000 0x1000>;
> + dmas = <&dac_tx_dma 0>;
> + dma-names = "tx";
> + #io-backend-cells = <0>;
> + clocks = <&ref_clk>;
> + dac {
> + compatible = "adi,ad3552r";
> + reset-gpios = <&gpio0 92 1>;
> + io-backends = <&backend>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + channel@0 {
> + reg = <0>;
> + adi,output-range-microvolt = <(-10000000) (10000000)>;
> + };
> + };
> + };
> +
> ...
>
