On Thu, Sep 05, 2024 at 05:17:30PM +0200, Angelo Dureghello wrote: > The serie comes from the previously discussed RFC, that i > converted to a normal patch from this v2. > > Purpose is to add ad3552r AXI DAC (fpga-based) support. > > The fpga DAC IP has been created to reach the maximum speed > (33MUPS) supported from the ad3552r. To obtain the maximum > transfer rate, the custom module has been implemented using > the QSPI lines in DDR mode, using a dma buffer. > > The design is actually using the DAC backend since the register > map is the same of the generic DAC IP, except for some customized > bitfields. For this reason, a new "compatible" has been added > in adi-axi-dac.c. > > Also, backend has been extended with all the needed functions > needed for this use case, keeping the names gneric. > > Note: the following patch is actually for linux-iio/testing > --- > Changes in v2: > - use unsigned int on bus_reg_read/write > - add a compatible in axi-dac backend for the ad3552r DAC IP > - minor code alignment fixes > - fix a return value not checked > - change devicetree structure setting ad3552r-axi as a backend > subnode > - add synchronous_mode_available in the ABI doc Please give reviewers a chance to response to in-progress discussion on a version before sending a new one. I've left a couple of responses to v1 that I only had a chance to reply to today due to travel.
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