On 9/4/2024 5:36 AM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2024-09-03 07:08:07)
On Tue, 3 Sept 2024 at 17:00, Jie Luo <quic_luoj@xxxxxxxxxxx> wrote:
On 9/3/2024 2:39 AM, Dmitry Baryshkov wrote:
On Mon, Sep 02, 2024 at 11:33:57PM GMT, Jie Luo wrote:
On 8/31/2024 6:24 AM, Stephen Boyd wrote:
Quoting Jie Luo (2024-08-30 09:14:28)
Hi Stephen,
Please find below a minor update to my earlier message on clk_ops usage.
Ok. Next time you can trim the reply to save me time.
OK.
On 8/28/2024 1:44 PM, Jie Luo wrote:
On 8/28/2024 7:50 AM, Stephen Boyd wrote:
Quoting Luo Jie (2024-08-27 05:46:00)
+ case 48000000:
+ val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
+ break;
+ case 50000000:
+ val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
+ break;
+ case 96000000:
+ val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
+ val &= ~CMN_PLL_REFCLK_DIV;
+ val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
+ break;
+ default:
+ return -EINVAL;
+ }
Why isn't this done with struct clk_ops::set_rate() or clk_ops::init()?
OK, I will move this code into the clk_ops::init().
This code is expected to be executed once for initializing the CMN PLL
to enable output clocks, and requires the parent clock rate to be
available. However the parent clock rate is not available in the
clk_ops::init(). Hence clk_ops::set_rate() seems to be the right option
for this. Please let us know if this approach is fine. Thanks.
Sure. It actually sounds like the PLL has a mux to select different
reference clks. Is that right? If so, it seems like there should be
multiple 'clocks' for the DT property and many parents possible. If
that's the case then it should be possible to have something like
clocks = <0>, <&refclk>, <0>;
in the DT node and then have clk_set_rate() from the consumer actually
set the parent index in hardware. If that's all static then it can be
done with assigned-clock-parents or assigned-clock-rates.
Thanks Stephen. The CMN PLL block always uses a single input reference
clock pin on any given IPQ SoC, however its rate may be different on
different IPQ SoC. For example, its rate is 48MHZ on IPQ9574 and 96MHZ
on IPQ5018.
How many input pins are there on the hardware block? It makes sense that
only one pin would be used in practice, but I'm wondering if there are
multiple pins in general. Why is the field called CMN_PLL_REFCLK_INDEX
if it's not picking the reference clk desired (i.e. the pin that is
actually connected)?
We double confirmed with our HW design team today, there is only one
input PIN to CMN PLL hardware block which is always sourced from the
internal Wi-Fi hardware block.
Let me provide more details below on the function of this block, to
provide a clear picture of the clock functions involved.
Input clock
-----------
This input clock rate at the pin is usually 48 MHZ, but an input rate of
96 MHZ at this pin is also supported by the block. Below is a picture
showing how input clocks are used in CMNPLL.
48mhz(or 96mhz)--->IN-clk-pin--->IN-clk-divider->(final-IN-clk)-->
CMNPLL HW logic-->out-clks
As per the input reference clock at the pin, the divider value is
configured on it. The register field CMN_PLL_REFCLK_INDEX is only used
to configure the final input clock rate (after the divider is applied)
to the CMNPLL HW logic.
So in summary, there is only one input clock pin. The register field
name CMN_PLL_REFCLK_INDEX (from hardware register description) may be
confusing, but it is actually only used to indicate the final input
clock rate to the CMNPLL hardware logic. I will clarify this with
additional comments in the code.
Core clock
-----------
The CMNPLL hardware block runs at 12 GHZ clock. It is automatically
derived from the input clock and no configuration required.
Output clock
------------
The CMNPLL block generates the all the output clocks (For ex: the 353
MHZ clock to PPE) without any software configuration required. The
driver only configures the input clock rate as described above.
Your second suggestion seems more apt for this device. I can define the
DT property 'assigned-clock-parents' to configure the clock parent of
CMN PLL. The code for reference clock selection will be added in
clk_ops::set_parent(). Please let us know if this approach is fine.
What is the source of this clock? Can you call clk_get_rate() on this
input?
The source (parent clock) for CMN PLL is always from on-board Wi-Fi
block for any given IPQ SoC.
From the discussion so far, it seems there are two approaches possible
which I would like to summarize below to be clear. Please let us know
if this understanding or approach needs correction. Thanks.
1. clk_get_rate() requires the parent clock instance to be acquired by
devm_clk_get(). Per our understanding from Stephen's previous comment,
it is preferred that a clock provider driver (this) does not use the
_get_ APIs on the parent clock to get the rate. Instead the parent rate
should be passed to the clk_ops using parent data.
struct clk_parent_data doesn't pass parent rate information to the
clk_ops. I'd like you to not use any clk consumer APIs (clk.h) if
possible.
OK.
So the parent clock
should be specified in the DT using assigned-clock-parents property, and
can be accessed from the clk_ops::set_parent(). This seems like a more
reasonable method.
Yes, this makes sense if the clk actually has multiple possible parents.
Don't read the rate of the clk in the clk_ops::set_parent() callback
though. The callback should only program the hardware to select the
parent based on the index passed to the clk_op.
OK, understand. However it seems like set_parent() method may not be an
option since there is only one parent clock input pin.
If the clk only has one possible parent then it's different. I'd do it
through clk_ops::set_rate() and use assigned-clock-rates or just let the
first child clk of the PLL set the rate and configure the PLL by having
the PLL's determine_rate() callback figure out if the parent rate is
valid.
Given the description above on the input clock function and the fact
that there is a single parent clock, could you suggest whether the
clk_ops::set_rate()/'assigned-clock-rates' method can be used to
configure the input clock rate?
We also looked at the determine_rate() method suggested, and felt that
this may not be feasible for this hardware model. This is because there
are more than one possible input clock rates (48 MHZ and 96 MHZ), and
hence it would not be feasible to derive a required input clock rate
from the core clock rate (12 GHZ).
That register field with "index" makes me suspicious that this is a mux
that we're trying to hide behind the parent rate. Quite possibly that's
actually a hardware multiplier, i.e. l-val, and we need to set the index
to pick which multiplier is used to achieve whatever frequency is
desired for the PLL itself. I assume the 353MHz output clk is actually
the one that is deciding what the index should be, and the other ones
all fall out of the PLL somewhere else through a post-divider or
something.
As described previously, there is only input clock pin with two possible
input clock rates (48 MHZ and 96 MHZ), and the index field only selects
the final input clock rate after applying the divider. There is no mux
function in the hardware.
The CMNPLL block generates the all the output clocks for a given SoC
without any software configuration required. The output clocks and their
rates are different on the different IPQ SoC. For example, the output
clock to PPE (Packet Process Engine hardware block) is 353 MHZ on
IPQ9574 and 200 MHZ on IPQ5332. The input clock rate of CMN PLL on
these two IPQ SoC is the same, but the internal logic of CMN PLL
which differs per SoC type ensures that the right output clocks are
generated for the given SoC. There is no provision or need for
multiplier configuration by software, to generate the output clocks.
What frequency does the PLL run at?
The CMN PLL core clock runs at 12 GHZ.
assigned-clock-parents is necessary if there are multiple possible
parents. As you wrote that there is just one possible parent, then
there is no need to use it.
Stephen, your opinion?
2. Alternatively, if it is architecturally acceptable to use
devm_clk_get() and clk_get_rate() in this clock provider driver, we can
save this parent clock rate into a local driver data structure and then
access it from clk_ops::init() for configuring the PLL.
No, it isn't acceptable.
