Re: [PATCH 1/3] dt-bindings: gpio: spacemit: add support for K1 SoC

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Hi Krzysztof 

On 08:46 Wed 04 Sep     , Krzysztof Kozlowski wrote:
> On Wed, Sep 04, 2024 at 12:27:23AM +0000, Yixun Lan wrote:
> > The GPIO controller of K1 support basic functions as input/output,
> > all pins can be used as interrupt which route to one IRQ line,
> > trigger type can be select between rising edge, failing edge, or both.
> > There are four GPIO banks, each consisting of 32 pins.
> > 
> > Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx>
> > ---
> >  .../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 95 ++++++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml
> > new file mode 100644
> > index 0000000000000..db2e62fb452fd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml
> > @@ -0,0 +1,95 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SpacemiT K1 GPIO controller
> > +
> > +description: >
> 
> Drop >
> 
> > +  The controller's registers are organized as sets of eight 32-bit
> > +  registers with each set controlling a bank of up to 32 pins.  A single
> > +  interrupt is shared for all of the banks handled by the controller.
> > +
> > +maintainers:
> > +  - Yixun Lan <dlan@xxxxxxxxxx>
> 
> Maintainers go before description. Use example-schema as template.
> 
> > +
> > +properties:
> > +  $nodename:
> > +    pattern: '^gpio@[0-9a-f]+$'
> 
> 
> No, why? Drop.
> 
> > +
> > +  compatible:
> > +    items:
> 
> and you can drop items as well.
> 
> > +      - const: spacemit,k1-gpio
> > +
> > +  reg:
> > +    maxItems: 1
> > +    description: >
> 
> Drop >. Everywhere.
> 
> > +      Define the base and range of the I/O address space containing
> > +      the SpacemiT K1 GPIO controller registers
> 
> Redundant description, drop.
> 
> > +
> > +  ranges: true
> > +
> > +  "#gpio-cells":
> > +    const: 2
> > +    description: >
> > +      The first cell is the pin number (within the controller's
> > +      pin space), and the second is used for the following:
> > +      bit[0]: polarity (0 for active-high, 1 for active-low)
> 
> Rather refer to standard GPIO bindings header.
> 
> > +
> > +  gpio-controller: true
> > +
> > +  gpio-ranges: true
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +    description:
> > +      The interrupt shared by all GPIO lines for this controller.
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: gpio_mux
> > +
> > +  "#interrupt-cells":
> > +    const: 2
> > +    description: |
> > +      The first cell is the GPIO number, the second should specify
> > +      flags.  The following subset of flags is supported:
> > +      - bits[3:0] trigger type flags (no level trigger type support)
> > +        1 = low-to-high edge triggered
> > +        2 = high-to-low edge triggered
> > +      Valid combinations are 1, 2, 3
> 
> Hm? No, you must use standard interrupt flags, not custom ones.
> 
It should be same as standard flags, my intention here was try to say
the controller support edge trigger only, but no level trigger flags (4, 8)
should I just replace number to macro, and put it like this:

The value is defined in <dt-bindings/interrupt-controller/irq.h>
Only the following flags are supported:
    IRQ_TYPE_EDGE_RISING
    IRQ_TYPE_EDGE_FALLING
    IRQ_TYPE_EDGE_BOTH


> > +
> > +  interrupt-controller: true
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - gpio-controller
> > +  - '#gpio-cells'
> > +  - interrupts
> > +  - interrupt-names
> > +  - interrupt-controller
> > +  - '#interrupt-cells'
> 
> Use consistent quotes. Either ' or ".
> 
> > +
> > +additionalProperties: false
> 
> Best regards,
> Krzysztof

Ack for other comments, will address them in next version, thanks

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55




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